Method for fabricating an integrated circuit with a transistor electrode

ABSTRACT

Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to semiconductor circuits, and moreparticularly to wells used in semiconductor circuits.

[0002] Some semiconductor circuits use wells biased at a predeterminedvoltage to obtain needed functionality or performance characteristics.For example, biased wells can be used to isolate transistors from eachother. Thus, in some dynamic random access memories (DRAMs), NMOStransistors of DRAM cells are formed in a P-well formed in a biased deepN well (DNW) that isolates the P well from the P doped substrate. The Pwell itself is biased at a lower voltage than the substrate. Hence, thebody regions of DRAM cell transistors in the P well are biased at alower voltage than the body regions of NMOS transistors of read/writecircuitry (for example, of sense amplifiers) that are fabricated in thesubstrate. The lower bias voltage in the P well reduces the leakagecurrent through the DRAM cell transistors. The leakage current throughthese transistors is of concern because it could discharge the cells. Atthe same time, the lower bias voltage is not suitable for read/writeNMOS transistors because the lower bias voltage would make thesetransistors slower. (Of note, the leakage current is not as big aconcern for the read/write transistors as for the DRAM celltransistors.) The biased DNW isolates the DRAM cell transistors from theread/write transistors.

[0003] In order to improve the electrical contact between a voltagesource biasing the DNW and the DNW itself, the DNW is provided with alow-resistance, heavily-doped N+ contact region located at the substratesurface. The N+ contact region is formed in a separate N well whichitself is formed in the DNW. The reason for the separate N well is asfollows.

[0004] One of the DRAM fabrications steps is a channel stop implant. Thechannel stop implant is a P-type implant performed into the NMOStransistor active areas and into field isolation regions. The purpose ofthe channel stop implant is to increase the punch-through voltages ofNMOS transistors and the punch-through and threshold voltages ofparasitic field transistors. The channel stop implant is blocked from Nwells in which PMOS transistors are formed. To simplify mask generation,the mask for the channel stop implant is made to be a reverse of themask used for the N-type implant that creates the N wells. Thus, thechannel stop implant is implanted precisely into those areas which areblocked from the N-well implant.

[0005] Besides the N wells containing the PMOS transistors, the channelstop implant is also blocked from the N+ contact region used to bias theDNW. This is done to prevent the channel stop P-type dopant fromimpeding electrical contact between the N+ contact region and the DNW.In order to enable the channel stop implant mask to be the reverse ofthe N well mask and still to block the channel stop implant from theN+contact region, the N+ contact region is formed in the separate N wellwhich is formed with the same N well mask as used for the N wellscontaining the PMOS transistors.

[0006] It is desirable to reduce spacings associated with wells in theintegrated circuit. Of note, a minimal spacing is typically requiredbetween a well and transistors outside the well. For example, in DRAMs aminimal spacing is required between the DNW and read/write circuitrytransistors. It is desirable to reduce such spacings.

SUMMARY OF THE INVENTION

[0007] According to the present invention, integrated circuit spacingrequirements are reduced. In some embodiments, spacing requirementsbetween wells and transistors outside the wells are eliminated.Therefore, the integrated circuit size can be reduced.

[0008] More particularly, in some embodiments, the separate N wellscontaining the N+ contact regions in the DNWs are eliminated. This ismade possible by modifying the channel stop mask not to be a reverse ofthe N well mask.

[0009] Further, spacing requirements between wells and transistorsoutside the wells are eliminated as follows. When transistors outsidethe well (e.g., a DNW) are laid out, the transistor placed adjacent tothe well is a transistor that can be used to bias the well. Thistransistor couples a predetermined voltage from one of its electrodes tothe other. For example, in a DRAM, this transistor can be a prechargetransistor that couples a predetermined voltage to a bit line toprecharge the bit line before a memory access (e.g., a memory readoperation). The predetermined voltage is also suitable to bias the well.The transistor electrode that receives the predetermined voltage is atleast partially inside the well, biasing the well to the predeterminedvoltage. Therefore, the minimal spacing requirement between the well andthe transistor is eliminated.

[0010] In some DRAM embodiments, the channel stop implant mask blocks atleast a portion of an area in which the DNW overlaps the prechargetransistor drain region. Hence, the channel stop P dopant is preventedfrom impeding the electrical contact between the DNW and the drainregion.

[0011] In some embodiments, P and N conductivity types are reversed.

[0012] Other features of the invention are described below. Theinvention is defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block diagram of a DRAM according to the presentinvention.

[0014]FIG. 2 shows a cross-section of a portion of the DRAM of FIG. 1.

[0015]FIGS. 3A, 3B are a circuit diagram of a portion of the DRAM ofFIG. 1.

[0016]FIGS. 4A, 4B are a top layout view of the portion of the DRAM ofFIG. 1.

[0017]FIGS. 5 and 6 are cross-section illustrations of the DRAM of FIG.1 in the process of fabrication.

[0018]FIG. 7 is a cross-sectional view showing drawn dimensions in someembodiments of FIG. 1.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0019]FIG. 1 shows an integrated DRAM 110. Memory arrays 120.1, 120.2 inDRAM 110 alternate with read/write (R/W) circuitry blocks 130.1, 130.2,130.3 along the horizontal direction in FIG. 1 (the memory columndirection). Each memory array 120 is surrounded on the left and right byR/W circuitry blocks 130. Each memory array 120 is an array of memorycells. Each cell includes an NMOS transistor 210 (FIG. 2). Sourceregions 210S and drain regions 210D of transistors 210 of each memoryarray are formed in one or more P wells 216. Each P well 216 is formedin a corresponding deep N well (DNW) 220.

[0020] Drain 210D of each transistor 210 is connected to a bit line BL(or a complimentary bit line {overscore (BL)}, not shown in FIG. 2).Source 210S is connected to a memory capacitor 226 which is alsoconnected to a reference voltage VREF. P well 216 is biased to anegative voltage, −1.0V in some embodiments in which VCC=3.3V, to reduceleakage through transistors 210. Deep N well 220 is biased to a positivevoltage HVCC (half VCC) to isolate the P well 216 from P substrate 230.VCC is 3.3V or 5.0V in some embodiments.

[0021] In an adjacent read/write circuitry block 130 on the right ofmemory array 120 in FIG. 2, the transistor adjacent to DNW 220 is a bitline precharge transistor 236. Drain 236D of transistor 236 is connectedto the same voltage source HVCC that biases the deep N well 220. Source236S is connected to a bit line BL (or {overscore (BL)}). Gate 236Greceives an equalization signal EQ. Signal EQ is asserted high before amemory access operation to precharge the bit lines to HVCC.

[0022] A portion of drain 236D is inside DNW 220 so that the DNWoverlaps the drain 236D. Therefore, no minimal spacing is requiredbetween the R/W circuitry block 130 and the deep N well.

[0023] Similarly, in R/W block 130 on the left of the memory array (notshown in FIG. 2), a bit line precharge transistor has a drain regionoverlapping DNW 220. The drain region is connected to HVCC. Therefore,no minimal spacing is required.

[0024] In some embodiments, the drains of the bit line prechargetransistors 236 are the only N+ contact regions in the DNW that connectthe DNW to HVCC.

[0025] As seen in FIG. 1, DRAM 110 includes four boundaries betweenmemory arrays 120 and R/W circuitry blocks 130. Hence, four minimalspacings are eliminated. The number of spacings eliminated increaseswith the number of memory arrays. Some 4 Mb DRAMs include 16 memoryarrays, and hence 32 boundaries between memory arrays and read/writecircuitry blocks. Significant size reduction is therefore achieved.

[0026] In FIG. 1, memory columns and their respective bit lines BL,{overscore (BL)}, extend horizontally. Memory rows and their respectiveword lines WL extend vertically. Each memory array 120.i is subdividedinto a number of identical memory blocks M-i.j. (A circuit diagram ofblock M-1.2 is shown in FIG. 3A.) Each memory block M-i.j is a singlecolumn of memory array 120.i. Each word line WL of memory array 120.iruns through all blocks M-i.j of the array. Only one pair of bit linesBL, {overscore (BL)} runs through any given memory block M-i.j.

[0027] The bit line pair BL, {overscore (BL)} of block M-i.j isconnected to a read/write block RW-k.j (FIGS. 1-3) in an adjacent R/Wcircuitry block 130.k (where k=i or k=i+1) in a staggered fashion. Thus,the bit lines of memory block M-1.1 are connected to read/write block(RW block) RW-1.1 on the left of memory array 120.1. The bit lines ofmemory block M-1.2 are connected to RW block RW-2.2 on the right ofmemory array 120.1, and so on. Block RW-2.2 is also connected to memoryblock M-2.2. Additional details of this staggered architecture aredescribed in U.S. patent application “DRAM With Staggered Shared BitLine Sense Amplifier Architecture”, attorney docket number M-3880 US,filed by Li-Chun Li et al. on Dec. 3, 1996 and incorporated herein byreference.

[0028] In memory block M-1.2 (FIG. 3A), and hence in every memory blockM-i.j, a memory cell is located at the intersection of bit line BL withevery other word line WL, and at the intersection of bit line {overscore(BL)} with each of the remaining word lines. The gate of each memorycell transistor 210 is connected to a respective word line WL, and thedrain is connected to a respective bit line BL or {overscore (BL)}.

[0029] All memory cell transistors 210 of a single memory array 120 areformed in the same P well 216 located in the same deep N well 220 (FIG.2).

[0030] As shown in FIGS. 3A, 3B, RW block RW-1.2 includes: (1) prechargeblock 310 (FIG. 3A) for precharging the bit line segments runningthrough memory block M-1.2; (2) sensing block 314 (FIG. 3B) including asense amplifier 320; and (3) precharge block 326 for precharging the bitline segments of memory block M-2.2. All the RW blocks RW-i.j areidentical to each other, except that the leftmost blocks RW-1.j omit theprecharge block 310, and the rightmost blocks RW-3.j omit prechargeblock 326.

[0031] In precharge block 310, precharge transistor 236 (FIGS. 2, 3A)has its drain connected to a metal-1 line HVCC-M1 running vertically (inthe plan view of FIGS. 1, 3A) through all the RW blocks in the R/Wcircuitry 130.2 (i.e. through blocks RW-2.2, RW-2.4). This metal-1 lineHVCC-M1 carries the constant voltage HVCC. The source of transistor 236is connected to bit line BL. The gate is connected to a metal-1 lineEQ-M1.

[0032] This line carries equalization signal EQ. Metal line EQ-M1 runsvertically through all the RW blocks of R/W circuitry 130.2.

[0033] Metal line EQ-M1 is connected also to the gate of NMOSequalization transistor 330 interconnecting the bit lines BL, {overscore(BL)}.

[0034] NMOS transistors 334, 340 connect bit line segments BL,{overscore (BL)} of memory block M-1.2 to respective bit line segmentsBL, {overscore (BL)} of sensing block 314 (FIG. 3B). Similar NMOStransistors 344, 350 connect the bit line segments of sensing block 314to respective bit line segments of memory block M-2.2. The gates oftransistors 334, 340 receive signal SS1 distributed on a verticalmetal-1 line SS1-M1. The gates of transistors 344, 350 receive signalSS2 distributed on a vertical metal-1 line SS2-M1. Lines SS1-M1, SS2-M1run through all the RW blocks of R/W circuitry 130.2. When signal SS1 isasserted high, sense amplifier 320 amplifies the signals from memoryblock M-1.2. When signal SS2 is asserted high, sense amplifier 320amplifies signals from memory block M-2.2. At most one of signals SS1,SS2 is high at any given time.

[0035] In sensing block 314, bit line BL is connected to a source/drainregion of NMOS pass transistor 354. The other source/drain region ofpass transistor 354 is connected to data bit output line {overscore(DB)}. Bit line {overscore (BL)} is connected to a source/drain regionof pass transistor 360 whose other source/drain region is connected tocomplimentary data bit output line DB. The gates of transistors 354, 360receive a column select signal YS. Data lines {overscore (DB)}, DB aremetal-1 lines running vertically through all the RW blocks of R/Wcircuitry 130.2.

[0036] PMOS transistors 364, 370 and NMOS transistors 374, 380 form twocross-coupled latches which form sense amplifier 320. Bit line BL isconnected to the gates of transistors 364, 374, and the drains oftransistors 370, 380. Bit line {overscore (BL)} is connected to thegates of transistors 370, 380, and the drains of transistors 364, 374.The sources of PMOS transistors 364, 370 are connected to a verticalmetal-2 line SLP. The sources of NMOS transistors 374, 380 are connectedto a vertical metal-2 line SLN. Lines SLP, SLN run through all the RWblocks of R/W circuitry 130.2. During amplification, line SLP isconnected to a positive voltage, and line SLN is connected to ground.During precharge, both lines SLP, SLN are connected to the sameprecharge voltage HVCC. The sense amplifier operation and timing aredescribed in U.S. patent application “Charging a Sense Amplifier”, Ser.No. 08/760,121, filed Dec. 3, 1996 by L. Liu et al. and incorporatedherein by reference.

[0037] Precharge block 326 is similar to block 310. In particular, block326 includes NMOS equalization transistor 381 connected between the bitlines BL, {overscore (BL)} and NMOS precharge transistor 383 connectedto bit line BL. The drain of transistor 383 is connected to a verticalmetal-1 line receiving the voltage HVCC and running through all the RWblocks of circuitry 130.2. The gates of transistors 381, 383 receiveequalization signals EQ provided on a vertical metal-1 line runningthrough all the RW blocks of circuitry 130.2. The drain of transistor383 overlaps with the deep N well (not shown) of memory block M-2.2.

[0038]FIGS. 4A, 4B are a layout view showing masks used to manufacturethe blocks 310, 314. DRAM 110 includes four polysilicon layers and twometal layers over the polysilicon layers. Bit lines BL, {overscore (BL)}are formed from the fourth polysilicon layer (“poly 4”). The bit lineboundaries are shown by dashed lines.

[0039] Stippled areas are mask openings through which N+ or P+ implantsare performed into substrate 230. Stippled region 210S is the N+ sourceregion of transistor 210 of the rightmost memory cell of memory blockM-1.2. See also FIG. 2. In capacitors 226 (FIG. 2), the capacitor platesconnected to memory cell transistors 210 are formed from the secondpolysilicon layer (not shown). The capacitor plate connected to voltageVREF is formed from the third polysilicon layer (not shown). This plateis shared by a number of memory blocks in a memory array. This poly-3plate is interrupted between some memory blocks M-i.j of the array toallow metal-1 word lines WL to contact poly-1 word lines WL (each wordline WL includes a metal-1 line running over a poly-1 line).

[0040] Stippled region 410 (FIG. 4A) includes N+ drain 236D of prechargetransistor 236.

[0041] Metal-1 line HVCC-M1 contacts drain region 236D in contact region418. (In region 418, line HVCC-M1 contacts a doped poly-4 region. Thepoly-4 region contacts the drain region.)

[0042] Metal-1 line EQ-M1 contacts a poly-1 line EQ-P1 in region 422.Poly-1 line EQ-P1 provides the gates for transistors 236, 330 (FIG. 3A).

[0043] Poly-1 line SS1-P1 provides the gates of transistors 334, 340.Line SS1-P1 contacts metal line SS1-M1 in region 426. Bit lines BL,{overscore (BL)} contact the source/drain regions of transistors 334,340 in contact regions 430.

[0044] Poly-1 line YS-P1 provides the gates of pass transistors 354,360. Poly-1 line YS-P1 contacts a metal-1 region in contact region 434.The metal-1 region contacts a metal-2 region which provides Y-selectsignal YS. Stippled region 440 includes source and drain regions oftransistor 360. (Region 440 is a mask opening through which the dopantis implanted. This implant is also masked by poly-1 line YS-P1, causingthe source and drain regions to be spaced from each other.) Asource/drain region of transistor 360 contacts the metal-1 line DB inregion 444.

[0045] Similarly, stippled region 450 includes the source and drainregions of transistor 354 of RW block RW-2.2 and of transistor 354 ofthe next RW block RW-2.4. Poly-1 line YS2-P1 provides the gates of thepass transistors of RW block RW-2.4. The common source/drain region oftransistors 354 of the two RW blocks contacts the data line {overscore(DB )} in contact region 454.

[0046] Bit lines BL, {overscore (BL)} contact the source/drain regionsof transistors 360, 354 in contact regions 455.

[0047] In FIG. 4B, poly-1 line 364-P1 extending essentially directlybelow the bit line {overscore (BL)} provides the gate of transistor 364.Poly-1 line 370-P1 extending essentially directly below the bit line BLprovides the gate of transistor 370. Stippled region 460 includes the P+sources and drains of the two PMOS transistors. Line 370-P1 contacts bitline {overscore (BL)} in contact region 464. Poly-1 line 364-P1 contactsbit line BL and the drain of transistor 370 in contact region 468. Bitline {overscore (BL)} contacts the drain of transistor 364 in contactregion 472. Metal-2 line SLP (not shown in FIG. 4B) contacts the commonsource of transistors 364, 370 in contact region 476.

[0048] Poly-1 line 374-P1 provides the gate of transistor 374. Poly-1line 380-P1 provides the gate of transistor 380. The two poly-1 linesextend between the bit lines essentially in parallel with the bit lines.Poly-1 line 380-P1 contacts bit line {overscore (BL)} in contact region480. Poly-1 line 374-P1 contacts bit line BL in contact region 482.

[0049] Stippled region 484 includes the sources and drains oftransistors 374, 380. Bit line BL contacts the drain of transistor 380in contact regions 486. Bit line {overscore (BL)} contacts the drain oftransistor 374 in contact regions 490. Metal-2 line SLN (not shown)contacts the common source of transistors 374, 380 in contact region494.

[0050] Bit lines BL, {overscore (BL)} contact the source/drain regionsof transistors 344, 350 (FIG. 3B) in contact regions 430 (FIG. 4B).Transistors 344, 350 are not shown in FIG. 4B.

[0051]FIG. 5 shows the beginning stages of fabrication of DRAM 110.Wafer 230 doped with boron has a doping concentration of 3×10¹⁵ cm⁻³.Initial silicon dioxide layer 510 is grown by thermal oxidation to athickness of 300 to 1000 nm. Oxide 510 is patterned by standardphotolithographic techniques to expose a region 520 into which dopantswill be implanted for P well 216 and DNW 220.

[0052] A protective silicon dioxide layer 530 is grown by thermaloxidation to a thickness of 30 to 300 nm (100 nm in some embodiments).Phosphorous is implanted into region 520 at the energy 180 keV to createDNW 220. The ion dose is 1 to 9 times 10¹³ atoms/cm² (1.5×10¹³ atoms/cm²in some embodiments.)

[0053] Phosphorous is driven in by heating the wafer in nitrogenatmosphere at a temperature of 1150° C. for 510 to 1000 minutes (950minutes in some embodiments). The deep N well diffuses laterally anddownward as shown in FIG. 6.

[0054] A blanket etch removes protective oxide 530 and a small portionof oxide 510. Protective silicon dioxide 610 is grown thermally to athickness of 30 to 300 nm (100 nm in some embodiments) by wet oxidationperformed at 950° C. for 10 to 60 minutes. Boron is implanted at anenergy of 30 to 180 keV (60 keV in some embodiments to form P well 216.The ion dose is 1×10¹³ to 9×10¹³cm⁻² (2×10 ¹³ cm⁻² in some embodiments).

[0055] Then oxide layers 510, 610 are removed. A protective 100 nm layerof silicon dioxide (“third protective oxide”, not shown) is grown by wetoxidation performed at 950° C. for 10 to 60 minutes. Photoresist (notshown) is deposited and patterned to expose N well regions 620 (FIG. 2)in which the PMOS transistor 370 and other PMOS transistors willbe-formed. Phosphorous is implanted at an energy of 30 to 180 keV toform the N wells. The ion dose is 1×10¹³ to 9×10¹³cm⁻² (1.2×10¹³ cm⁻² insome embodiments). Then a well drive-in step is performed at atemperature of 1150° C. for 200 to 800 minutes (250 minutes in someembodiments). The resulting depth of DNWs 220 is about 5 μm. The depthof P wells 216 is 2 μm. The depth of N wells 620 is 3 μm. The distancedw between the right edge of P well 216 and the right edge of respectiveDNW 220 is 2 μm.

[0056] The third protective oxide is removed. 470 nm thick field oxideregions 630 are grown between transistor active areas by LOCOS oxidationperformed at 1000° C. for 90 minutes using methods known in the art.

[0057] A 30 nm sacrificial layer of silicone dioxide (not shown) isgrown by wet oxidation performed at 850° C. for 40 minutes. Blanket ionimplantation of BF2 is performed through this sacrificial oxide at anenergy of 70 keV to adjust transistor threshold voltages. The ion doseis 3.2×10¹² cm⁻².

[0058] Then a deep P type implant (channel stop implant) is performedinto NMOS transistor active regions to enhance the P type dopantconcentration under the NMOS transistors and the field oxide regions.The resulting P- channel stop regions are shown at 640. Regions 640increase the punch-through voltages of NMOS transistors and parasitictransistors formed under field oxide 630. Regions 640 also increase theparasitic transistor threshold voltages. Regions 640 are formed byimplanting boron at the energy 120 keV. The ion dose is 8×10¹²atoms/cm². The implant mask protects N wells 620 during this implant.The implant mask also protects regions CN of equalization transistordrains 236D. Each region CN overlaps an area in which the respectivedrain 236D meets the respective DNW 220. Protecting the regions CN fromthe channel stop implant serves to improve the electrical contactbetween drains 236D and DNWs 220.

[0059] In some embodiments, the channel stop implant mask is the reverseof the N well 620 mask except that the channel stop implant mask alsocovers regions CN.

[0060] Each region CN is spaced from the respective gate 236G. Thisspacing allows a portion 640.1 of channel stop region 640 to extendunder the drain 236D, thus increasing the punch-through voltage oftransistor 236. Each region CN is also spaced from the edge of therespective drain 236D where the drain meets field oxide 630 (the leftedge of drain 236D in FIG. 2). This spacing allows a portion 640.2 ofchannel stop region 640 to extend from under the field oxide to a regionunder the drain 236D. This helps to improve the punch-through voltageand the threshold voltage of the field transistor formed at the locationof oxide 630.

[0061] In some embodiments, after formation of the implant mask used toform channel stop regions 640, but before the boron implantation formingthe channel stop regions, another boron implant is performed through thesacrificial oxide at an energy of 30 keV to adjust the thresholdvoltages of NMOS transistors. The ion dose of this implant is 2×10¹²cm⁻².

[0062] After the channel stop implant, the sacrificial oxide is removed.

[0063] Gate oxide (not shown) is grown to a thickness of 5 to 18 nm (8nm in some embodiments) by oxidizing the structure at 700 to 1000° C.(850° C. in some embodiments) for 10 to 60 minutes. Polysilicon orpolycide gates of transistors 210, 236, 370, and other transistors, areformed by known techniques.

[0064] Phosphorous is ion-implanted at 25 keV to form LDD regions ofNMOS transistors. The ion dose is 2×10¹³ cm⁻². Then pocket ionimplantation of boron is performed at an angle of 25° and an energy of60 keV into regions underlying NMOS sources and drains, to increase theNMOS punch-through voltages. The pocket implant ion dose is 1.2×10¹³cm⁻². These two implants—NMOS LDD and P-type pocket—are performed usingthe same photoresist mask (“NMOS LDD mask”, not shown) patterned bystandard photolithographic techniques. The mask covers regions LN one ofwhich is shown in FIG. 2. Each region LN covers the region CN andextends to the adjacent field oxide region 630 separating the respectivedrain 236D from the respective P well 216. By covering the regions LN,the mask blocks the pocket-implant boron from areas in which the drainregions 236D meet the respective DNWs 220. Thus, the mask helps toimprove the contact between drain regions 236D and DNWs. At the same,the mask exposes a portion of the drains 236D adjacent the respectivegates 236G and also exposes the source regions 236S.

[0065] Pocket implants are described in U.S. Pat. No. 5,618,740 entitled“Method of Making CMOS Output Buffer with Enhanced ESD Resistance”,issued Apr. 8, 1997 to T. Huang and incorporated herein by reference.

[0066] BF2 is implanted to form LDD regions of PMOS transistors such astransistor 370. A pocket implant of phosphorous is performed into thePMOS transistor regions to increase their punch-through voltages. A 100nm layer of silicone nitride (not shown) is deposited by LPCVD andetched to form spacers on transistor gate sidewalls. The silicon nitridedeposition temperature is 780° C., and the deposition time is 40 mins. A20 nm layer of silicone dioxide (not shown) is grown at 875° C. onexposed silicone surfaces. Arsenic and BF2 are implanted in successiveion implantation steps. The arsenic implant forms heavily doped portionsof NMOS source/drain regions. The BF2 implant forms heavily dopedportions of PMOS source/drain regions and also forms one or more P+contact regions (not shown) in each P well 216. The P+ contact regionswill contact a voltage source that will bias the P-wells. In someembodiments, the mask used in the BF2 implant is the reverse tone of theNMOS LDD mask, except that both the NMOS LDD mask and the BF2 mask blockthe regions LN.

[0067] Remaining fabrication steps are known in the art.

[0068] The dopant concentration in DNWs 220 is 1×10¹⁶ atoms/cm³. Thedopant concentration in drains 236D is 1×10²⁰ atoms/cm³. The higherdopant concentration in the drain regions improves the electricalcontact between DNWs 220 and doped poly-4 regions (not shown) contactingthe drains 236D and also contacting the metal-1 lines HVCC-M1.

[0069]FIG. 7 illustrates some drawn mask dimensions in the cross sectionof FIG. 2. The lateral distance d1 between the right edge of therightmost source region 210S in a P well 216 and the right edge of therespective DNW 220/P well 216 mask opening (corresponding to the leftedge of oxide 510 in FIG. 5) is only 0.45 μm. This spacing is small dueto elimination of a separate N+ contact region in the DNW and of aseparate N well containing the N+ contact region. The distance d2between the right edge of the DNW mask opening and the left edge of themask opening for drain region 236D is 1.5 μm. The drawn distance d3between the left edge of the region 236D and the left edge of the regionCN is 0.4 μm. The width d4 of each region CN is 3.1 μm. The distance d5between the right edge of the region CN and the left edge of gate 236Gis 1.0 μm.

[0070] The distance d6 between the left edges of region LN and drain236D is 1.0 μm. The rights edges of regions LN, CN coincide.

[0071] In this embodiment, DNW 220 diffuses laterally after implantationby 75-80% of the DNW depth. Thus, if the DNW depth is 5 μm, the DNWdiffuses laterally by 3.75 μm to 4 μm. The minimal photolithographicline width is 0.5 μm, and the maximum alignment error is 0.6 μm. Theminimal spacing between the DNW mask and the gate of the nearesttransistor is only d2+d3+d4+d5=6 μm.

[0072] The above embodiments illustrate but do not limit the invention.In particular, the invention is not limited by any particulardimensions, fabrication techniques, temperatures, energies, or otherprocess parameters, or by layer compositions or layout. The invention isnot limited to DRAMs or any other particular circuitry. Otherembodiments and variations are within the scope of the invention asdefined by the following claims.

1-10. (canceled).
 11. A method for fabricating an integrated circuit,the method comprising: introducing a dopant of a first conductivity typeinto a semiconductor substrate to form a first well; and forming atransistor T1 having first and second electrodes of the firstconductivity type, the first electrode having at least a portion insidethe first well, wherein the first electrode is connected to a voltagefor: (1) biasing the first well, and (2) coupling the voltage to thesecond electrode when the transistor is on.
 12. The method of claim 11further comprising: introducing a dopant of a second conductivity typeinto the first well to form a second well inside the first well; andforming one or more transistors T2 having electrodes of the firstconductivity type in the second well. 13-20. (canceled).
 21. The methodof claim 11 wherein the voltage is between about 1.6V and about 2.5V.22. The method of claim 11 wherein the dopant of a first conductivitytype comprises phosphorous.
 23. The method of claim 11 whereintransistor T1 further comprises a gate, wherein the gate receives anequalization signal.
 24. The method of claim 12 wherein the dopant of asecond conductivity type comprises boron.
 25. The method of claim 12wherein at least one of the electrodes of the first conductivity type inthe second well is connected to a capacitor.
 26. The method of claim 12wherein at least one of the electrodes of the first conductivity type inthe second well is connected to a bit line, wherein the bit line isfurther connected to the second electrode of transistor T1.
 27. Themethod of claim 12 wherein the second well contains electrodes of adynamic random access memory (DRAM) cell transistor.
 28. The method ofclaim 12 further comprising: introducing a dopant of the firstconductivity type into the semiconductor substrate to form a third wellof the first conductivity type, wherein the third well is for holdingsecond-conductivity-type electrodes of one or more transistors, andwherein the third well does not overlap with the first well.
 29. Themethod of claim 11, wherein the second electrode is outside of the firstwell.
 30. The method of claim 11, wherein the transistor T1 has achannel region of the second conductivity type.
 31. The method of claim11, wherein the first well is of the first conductivity type.
 32. Themethod of claim 12, wherein the second well is of the secondconductivity type.
 33. A method for fabricating an integrated circuit,the method comprising: introducing a dopant of a first conductivity typeinto a semiconductor substrate to form a first well of a firstconductivity type; and forming a transistor T1 having first and secondelectrodes of the first conductivity type, the first electrode having atleast a portion inside the first well and a portion outside the firstwell, wherein the first electrode is connected to a voltage for: (1)biasing the first well, and (2) coupling the voltage to the secondelectrode when the transistor is on.
 34. The method of claim 33 whereinthe portion of the first electrode outside the first well is in a regionof a second conductivity type.